Project Information                                   z:\tec\lab6\adder8v3.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/16/2007 11:56:23

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


Untitled


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

adder8v3  EPM7064LC44-7    17       9        0      41      31          64 %

User Pins:                 17       9        0  



Project Information                                   z:\tec\lab6\adder8v3.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clock' chosen for auto global Clock


Project Information                                   z:\tec\lab6\adder8v3.rpt

** FILE HIERARCHY **



|adder4:53|
|adder4:53|fa:41|
|adder4:53|fa:47|
|adder4:53|fa:53|
|adder4:53|fa:59|
|adder4:68|
|adder4:68|fa:41|
|adder4:68|fa:47|
|adder4:68|fa:53|
|adder4:68|fa:59|


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

***** Logic for device 'adder8v3' compiled without errors.




Device: EPM7064LC44-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

                                         R     
                                         E     
                                         S     
                                   c     E     
                                   l     R     
                       V  G  G  G  o  G  V     
              b  b  b  C  N  N  N  c  N  E  s  
              2  1  0  C  D  D  D  k  D  D  3  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
      b3 |  7                                39 | RESERVED 
      b4 |  8                                38 | s2 
      b5 |  9                                37 | s1 
     GND | 10                                36 | s0 
      b7 | 11                                35 | VCC 
      b6 | 12         EPM7064LC44-7          34 | RESERVED 
      a5 | 13                                33 | RESERVED 
      a4 | 14                                32 | RESERVED 
     VCC | 15                                31 | RESERVED 
      a3 | 16                                30 | GND 
      a2 | 17                                29 | cout 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              a  s  a  s  G  V  s  s  a  a  R  
              1  5  6  6  N  C  4  7  7  0  E  
                          D  C              S  
                                            E  
                                            R  
                                            V  
                                            E  
                                            D  


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   8/ 8(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32    10/16( 62%)   8/ 8(100%)  12/16( 75%)  15/36( 41%) 
C:    LC33 - LC48    16/16(100%)   5/ 8( 62%)  14/16( 87%)  22/36( 61%) 
D:    LC49 - LC64    15/16( 93%)   4/ 8( 50%)  12/16( 75%)  18/36( 50%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            25/32     ( 78%)
Total logic cells used:                         41/64     ( 64%)
Total shareable expanders used:                 31/64     ( 48%)
Total Turbo logic cells used:                   41/64     ( 64%)
Total shareable expanders not available (n/a):   7/64     ( 10%)
Average fan-in:                                  3.58
Total fan-in:                                   147

Total input pins required:                      17
Total output pins required:                      9
Total bidirectional pins required:               0
Total logic cells required:                     41
Total flipflops required:                       38
Total product terms required:                  109
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          31

Synthesized logic cells:                         3/  64   (  4%)



Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  27   (37)  (C)      INPUT               0      0   0    0    0    0    1  a0
  18   (21)  (B)      INPUT               0      0   0    0    0    0    1  a1
  17   (24)  (B)      INPUT               0      0   0    0    0    0    1  a2
  16   (25)  (B)      INPUT               0      0   0    0    0    0    1  a3
  14   (30)  (B)      INPUT               0      0   0    0    0    0    1  a4
  13   (32)  (B)      INPUT               0      0   0    0    0    0    1  a5
  20   (19)  (B)      INPUT               0      0   0    0    0    0    1  a6
  26   (36)  (C)      INPUT               0      0   0    0    0    0    1  a7
   4   (16)  (A)      INPUT               0      0   0    0    0    0    1  b0
   5   (14)  (A)      INPUT               0      0   0    0    0    0    1  b1
   6   (11)  (A)      INPUT               0      0   0    0    0    0    1  b2
   7    (8)  (A)      INPUT               0      0   0    0    0    0    1  b3
   8    (5)  (A)      INPUT               0      0   0    0    0    0    1  b4
   9    (4)  (A)      INPUT               0      0   0    0    0    0    1  b5
  12    (1)  (A)      INPUT               0      0   0    0    0    0    1  b6
  11    (3)  (A)      INPUT               0      0   0    0    0    0    1  b7
  43      -   -       INPUT  G            0      0   0    0    0    0    0  clock


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  29     41    C         FF   +  t        5      0   1    0    9    0    0  cout
  36     52    D         FF   +  t        0      0   0    0    1    0    0  s0
  37     53    D         FF   +  t        0      0   0    0    1    0    0  s1
  38     56    D         FF   +  t        0      0   0    0    1    0    0  s2
  40     62    D         FF   +  t        0      0   0    0    1    0    0  s3
  24     33    C         FF   +  t        0      0   0    0    3    0    0  s4
  19     20    B         FF   +  t        3      0   1    0    5    0    0  s5
  21     17    B         FF   +  t        9      0   0    0    7    0    0  s6
  25     35    C         FF   +  t        7      0   0    0   11    0    0  s7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     58    D       SOFT    s t        1      0   1    0    6    0    1  |adder4:53|fa:41|~33~1
   -     34    C       SOFT    s t        1      0   1    0    6    1    0  |adder4:68|fa:41|~33~1
   -     42    C       SOFT    s t        1      0   1    0    7    1    0  |adder4:68|fa:41|~33~2
 (41)    64    D       DFFE   +  t        0      0   0    1    0    0    5  maf10
   -     63    D       DFFE   +  t        0      0   0    1    0    0    5  maf11
   -     60    D       DFFE   +  t        0      0   0    1    0    0    4  maf12
   -     59    D       DFFE   +  t        0      0   0    1    0    0    2  maf13
 (28)    40    C       DFFE   +  t        0      0   0    1    0    0    5  mbf10
   -     39    C       DFFE   +  t        0      0   0    1    0    0    5  mbf11
   -     43    C       DFFE   +  t        0      0   0    1    0    0    4  mbf12
   -     44    C       DFFE   +  t        0      0   0    1    0    0    2  mbf13
 (33)    49    D       DFFE   +  t        4      1   1    0    8    5    2  pmf2
 (32)    48    C       DFFE   +  t        0      0   0    1    0    0    1  saf10
   -     45    C       DFFE   +  t        0      0   0    1    0    0    1  saf11
   -     47    C       DFFE   +  t        0      0   0    1    0    0    1  saf12
 (31)    46    C       DFFE   +  t        0      0   0    1    0    0    1  saf13
   -     50    D       DFFE   +  t        0      0   0    0    1    5    2  saf20
   -     38    C       DFFE   +  t        0      0   0    0    1    4    2  saf21
 (27)    37    C       DFFE   +  t        0      0   0    0    1    3    1  saf22
   -     27    B       DFFE   +  t        0      0   0    0    1    2    0  saf23
 (18)    21    B       DFFE   +  t        0      0   0    1    0    0    1  sbf10
   -     23    B       DFFE   +  t        0      0   0    1    0    0    1  sbf11
 (17)    24    B       DFFE   +  t        0      0   0    1    0    0    1  sbf12
   -     28    B       DFFE   +  t        0      0   0    1    0    0    1  sbf13
 (26)    36    C       DFFE   +  t        0      0   0    0    1    5    2  sbf20
 (20)    19    B       DFFE   +  t        0      0   0    0    1    4    2  sbf21
   -     18    B       DFFE   +  t        0      0   0    0    1    3    2  sbf22
   -     26    B       DFFE   +  t        0      0   0    0    1    2    0  sbf23
   -     61    D       DFFE   +  t        0      0   0    0    2    1    0  smf20
 (34)    51    D       DFFE   +  t        0      0   0    0    4    1    0  smf21
   -     54    D       DFFE   +  t        4      1   1    0    6    1    0  smf22
 (39)    57    D       DFFE   +  t        4      0   0    0    7    1    0  smf23


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC27 saf23
        | +----------------- LC21 sbf10
        | | +--------------- LC23 sbf11
        | | | +------------- LC24 sbf12
        | | | | +----------- LC28 sbf13
        | | | | | +--------- LC19 sbf21
        | | | | | | +------- LC18 sbf22
        | | | | | | | +----- LC26 sbf23
        | | | | | | | | +--- LC20 s5
        | | | | | | | | | +- LC17 s6
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC23 -> - - - - - * - - - - | - * - - | <-- sbf11
LC24 -> - - - - - - * - - - | - * - - | <-- sbf12
LC28 -> - - - - - - - * - - | - * - - | <-- sbf13
LC19 -> - - - - - - - - * * | - * * - | <-- sbf21
LC18 -> - - - - - - - - - * | - * * - | <-- sbf22

Pin
8    -> - * - - - - - - - - | - * - - | <-- b4
9    -> - - * - - - - - - - | - * - - | <-- b5
12   -> - - - * - - - - - - | - * - - | <-- b6
11   -> - - - - * - - - - - | - * - - | <-- b7
43   -> - - - - - - - - - - | - - - - | <-- clock
LC49 -> - - - - - - - - * * | - * * - | <-- pmf2
LC46 -> * - - - - - - - - - | - * - - | <-- saf13
LC50 -> - - - - - - - - * * | - * * - | <-- saf20
LC38 -> - - - - - - - - * * | - * * - | <-- saf21
LC37 -> - - - - - - - - - * | - * * - | <-- saf22
LC36 -> - - - - - - - - * * | - * * - | <-- sbf20


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC34 |adder4:68|fa:41|~33~1
        | +----------------------------- LC42 |adder4:68|fa:41|~33~2
        | | +--------------------------- LC41 cout
        | | | +------------------------- LC40 mbf10
        | | | | +----------------------- LC39 mbf11
        | | | | | +--------------------- LC43 mbf12
        | | | | | | +------------------- LC44 mbf13
        | | | | | | | +----------------- LC48 saf10
        | | | | | | | | +--------------- LC45 saf11
        | | | | | | | | | +------------- LC47 saf12
        | | | | | | | | | | +----------- LC46 saf13
        | | | | | | | | | | | +--------- LC38 saf21
        | | | | | | | | | | | | +------- LC37 saf22
        | | | | | | | | | | | | | +----- LC36 sbf20
        | | | | | | | | | | | | | | +--- LC33 s4
        | | | | | | | | | | | | | | | +- LC35 s7
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC34 -> - - - - - - - - - - - - - - - * | - - * - | <-- |adder4:68|fa:41|~33~1
LC42 -> - - - - - - - - - - - - - - - * | - - * - | <-- |adder4:68|fa:41|~33~2
LC45 -> - - - - - - - - - - - * - - - - | - - * - | <-- saf11
LC47 -> - - - - - - - - - - - - * - - - | - - * - | <-- saf12
LC38 -> * * * - - - - - - - - - - - - * | - * * - | <-- saf21
LC37 -> - * * - - - - - - - - - - - - * | - * * - | <-- saf22
LC36 -> * * * - - - - - - - - - - - * * | - * * - | <-- sbf20

Pin
14   -> - - - - - - - * - - - - - - - - | - - * - | <-- a4
13   -> - - - - - - - - * - - - - - - - | - - * - | <-- a5
20   -> - - - - - - - - - * - - - - - - | - - * - | <-- a6
26   -> - - - - - - - - - - * - - - - - | - - * - | <-- a7
4    -> - - - * - - - - - - - - - - - - | - - * - | <-- b0
5    -> - - - - * - - - - - - - - - - - | - - * - | <-- b1
6    -> - - - - - * - - - - - - - - - - | - - * - | <-- b2
7    -> - - - - - - * - - - - - - - - - | - - * - | <-- b3
43   -> - - - - - - - - - - - - - - - - | - - - - | <-- clock
LC49 -> * * * - - - - - - - - - - - * * | - * * - | <-- pmf2
LC50 -> * * * - - - - - - - - - - - * * | - * * - | <-- saf20
LC27 -> - - * - - - - - - - - - - - - * | - - * - | <-- saf23
LC21 -> - - - - - - - - - - - - - * - - | - - * - | <-- sbf10
LC19 -> * * * - - - - - - - - - - - - * | - * * - | <-- sbf21
LC18 -> * * * - - - - - - - - - - - - * | - * * - | <-- sbf22
LC26 -> - - * - - - - - - - - - - - - * | - - * - | <-- sbf23


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                       Logic cells placed in LAB 'D'
        +----------------------------- LC58 |adder4:53|fa:41|~33~1
        | +--------------------------- LC64 maf10
        | | +------------------------- LC63 maf11
        | | | +----------------------- LC60 maf12
        | | | | +--------------------- LC59 maf13
        | | | | | +------------------- LC49 pmf2
        | | | | | | +----------------- LC50 saf20
        | | | | | | | +--------------- LC61 smf20
        | | | | | | | | +------------- LC51 smf21
        | | | | | | | | | +----------- LC54 smf22
        | | | | | | | | | | +--------- LC57 smf23
        | | | | | | | | | | | +------- LC52 s0
        | | | | | | | | | | | | +----- LC53 s1
        | | | | | | | | | | | | | +--- LC56 s2
        | | | | | | | | | | | | | | +- LC62 s3
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC58 -> - - - - - - - - - - * - - - - | - - - * | <-- |adder4:53|fa:41|~33~1
LC64 -> * - - - - * - * * * - - - - - | - - - * | <-- maf10
LC63 -> * - - - - * - - * * * - - - - | - - - * | <-- maf11
LC60 -> * - - - - * - - - * * - - - - | - - - * | <-- maf12
LC59 -> - - - - - * - - - - * - - - - | - - - * | <-- maf13
LC61 -> - - - - - - - - - - - * - - - | - - - * | <-- smf20
LC51 -> - - - - - - - - - - - - * - - | - - - * | <-- smf21
LC54 -> - - - - - - - - - - - - - * - | - - - * | <-- smf22
LC57 -> - - - - - - - - - - - - - - * | - - - * | <-- smf23

Pin
27   -> - * - - - - - - - - - - - - - | - - - * | <-- a0
18   -> - - * - - - - - - - - - - - - | - - - * | <-- a1
17   -> - - - * - - - - - - - - - - - | - - - * | <-- a2
16   -> - - - - * - - - - - - - - - - | - - - * | <-- a3
43   -> - - - - - - - - - - - - - - - | - - - - | <-- clock
LC40 -> * - - - - * - * * * - - - - - | - - - * | <-- mbf10
LC39 -> * - - - - * - - * * * - - - - | - - - * | <-- mbf11
LC43 -> * - - - - * - - - * * - - - - | - - - * | <-- mbf12
LC44 -> - - - - - * - - - - * - - - - | - - - * | <-- mbf13
LC48 -> - - - - - - * - - - - - - - - | - - - * | <-- saf10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          z:\tec\lab6\adder8v3.rpt
adder8v3

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
a4       : INPUT;
a5       : INPUT;
a6       : INPUT;
a7       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
b4       : INPUT;
b5       : INPUT;
b6       : INPUT;
b7       : INPUT;
clock    : INPUT;

-- Node name is 'cout' = 'psf3' from file "adder8v3.tdf" line 11, column 56
-- Equation name is 'cout', location is LC041, type is output.
 cout    = DFFE( _EQ001 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ001 =  saf20 &  sbf20 &  _X001 &  _X002 &  _X003
         #  pmf2 &  _X001 &  _X002 &  _X003 &  _X004
         #  saf21 &  sbf21 &  _X001 &  _X003
         #  saf22 &  sbf22 &  _X003
         #  saf23 &  sbf23;
  _X001  = EXP(!saf22 & !sbf22);
  _X002  = EXP(!saf21 & !sbf21);
  _X003  = EXP(!saf23 & !sbf23);
  _X004  = EXP(!saf20 & !sbf20);

-- Node name is 'maf10' from file "adder8v3.tdf" line 10, column 6
-- Equation name is 'maf10', location is LC064, type is buried.
maf10    = DFFE( a0 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'maf11' from file "adder8v3.tdf" line 10, column 6
-- Equation name is 'maf11', location is LC063, type is buried.
maf11    = DFFE( a1 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'maf12' from file "adder8v3.tdf" line 10, column 6
-- Equation name is 'maf12', location is LC060, type is buried.
maf12    = DFFE( a2 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'maf13' from file "adder8v3.tdf" line 10, column 6
-- Equation name is 'maf13', location is LC059, type is buried.
maf13    = DFFE( a3 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'mbf10' from file "adder8v3.tdf" line 10, column 18
-- Equation name is 'mbf10', location is LC040, type is buried.
mbf10    = DFFE( b0 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'mbf11' from file "adder8v3.tdf" line 10, column 18
-- Equation name is 'mbf11', location is LC039, type is buried.
mbf11    = DFFE( b1 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'mbf12' from file "adder8v3.tdf" line 10, column 18
-- Equation name is 'mbf12', location is LC043, type is buried.
mbf12    = DFFE( b2 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'mbf13' from file "adder8v3.tdf" line 10, column 18
-- Equation name is 'mbf13', location is LC044, type is buried.
mbf13    = DFFE( b3 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'pmf2' from file "adder8v3.tdf" line 11, column 2
-- Equation name is 'pmf2', location is LC049, type is buried.
pmf2     = DFFE( _EQ002 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ002 =  maf10 &  mbf10 &  mbf13 &  _X005 &  _X006
         #  maf10 &  maf13 &  mbf10 &  _X005 &  _X006
         #  maf11 &  mbf11 &  _X005 &  _X007
         #  maf12 &  mbf12 &  _X007
         #  maf13 &  mbf13;
  _X005  = EXP(!maf12 & !mbf12);
  _X006  = EXP(!maf11 & !mbf11);
  _X007  = EXP(!maf13 & !mbf13);

-- Node name is 'saf10' from file "adder8v3.tdf" line 10, column 30
-- Equation name is 'saf10', location is LC048, type is buried.
saf10    = DFFE( a4 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf11' from file "adder8v3.tdf" line 10, column 30
-- Equation name is 'saf11', location is LC045, type is buried.
saf11    = DFFE( a5 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf12' from file "adder8v3.tdf" line 10, column 30
-- Equation name is 'saf12', location is LC047, type is buried.
saf12    = DFFE( a6 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf13' from file "adder8v3.tdf" line 10, column 30
-- Equation name is 'saf13', location is LC046, type is buried.
saf13    = DFFE( a7 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf20' from file "adder8v3.tdf" line 11, column 12
-- Equation name is 'saf20', location is LC050, type is buried.
saf20    = DFFE( saf10 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf21' from file "adder8v3.tdf" line 11, column 12
-- Equation name is 'saf21', location is LC038, type is buried.
saf21    = DFFE( saf11 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf22' from file "adder8v3.tdf" line 11, column 12
-- Equation name is 'saf22', location is LC037, type is buried.
saf22    = DFFE( saf12 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'saf23' from file "adder8v3.tdf" line 11, column 12
-- Equation name is 'saf23', location is LC027, type is buried.
saf23    = DFFE( saf13 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf10' from file "adder8v3.tdf" line 10, column 42
-- Equation name is 'sbf10', location is LC021, type is buried.
sbf10    = DFFE( b4 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf11' from file "adder8v3.tdf" line 10, column 42
-- Equation name is 'sbf11', location is LC023, type is buried.
sbf11    = DFFE( b5 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf12' from file "adder8v3.tdf" line 10, column 42
-- Equation name is 'sbf12', location is LC024, type is buried.
sbf12    = DFFE( b6 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf13' from file "adder8v3.tdf" line 10, column 42
-- Equation name is 'sbf13', location is LC028, type is buried.
sbf13    = DFFE( b7 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf20' from file "adder8v3.tdf" line 11, column 24
-- Equation name is 'sbf20', location is LC036, type is buried.
sbf20    = DFFE( sbf10 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf21' from file "adder8v3.tdf" line 11, column 24
-- Equation name is 'sbf21', location is LC019, type is buried.
sbf21    = DFFE( sbf11 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf22' from file "adder8v3.tdf" line 11, column 24
-- Equation name is 'sbf22', location is LC018, type is buried.
sbf22    = DFFE( sbf12 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'sbf23' from file "adder8v3.tdf" line 11, column 24
-- Equation name is 'sbf23', location is LC026, type is buried.
sbf23    = DFFE( sbf13 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'smf20' from file "adder8v3.tdf" line 10, column 54
-- Equation name is 'smf20', location is LC061, type is buried.
smf20    = DFFE( mbf10 $  maf10, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 'smf21' from file "adder8v3.tdf" line 10, column 54
-- Equation name is 'smf21', location is LC051, type is buried.
smf21    = DFFE( _EQ003 $  maf11, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ003 =  maf10 &  mbf10 & !mbf11
         # !maf10 &  mbf11
         # !mbf10 &  mbf11;

-- Node name is 'smf22' from file "adder8v3.tdf" line 10, column 54
-- Equation name is 'smf22', location is LC054, type is buried.
smf22    = DFFE( _EQ004 $  maf12, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ004 =  maf10 &  mbf10 & !mbf12 &  _X006
         #  maf11 &  mbf11 & !mbf12
         # !maf11 &  mbf12 &  _X008
         # !mbf11 &  mbf12 &  _X009;
  _X006  = EXP(!maf11 & !mbf11);
  _X008  = EXP( maf10 &  mbf10 &  mbf11);
  _X009  = EXP( maf10 &  mbf10);

-- Node name is 'smf23' from file "adder8v3.tdf" line 10, column 54
-- Equation name is 'smf23', location is LC057, type is buried.
smf23    = DFFE( _EQ005 $  _EQ006, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ005 =  _X010 &  _X011;
  _X010  = EXP(!maf13 &  mbf13);
  _X011  = EXP( maf13 & !mbf13);
  _EQ006 = !_LC058 &  _X012 &  _X013;
  _X012  = EXP( maf11 &  maf12 &  mbf11);
  _X013  = EXP( maf12 &  mbf12);

-- Node name is 's0' = 'smf30' from file "adder8v3.tdf" line 11, column 36
-- Equation name is 's0', location is LC052, type is output.
 s0      = DFFE( smf20 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 's1' = 'smf31' from file "adder8v3.tdf" line 11, column 36
-- Equation name is 's1', location is LC053, type is output.
 s1      = DFFE( smf21 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 's2' = 'smf32' from file "adder8v3.tdf" line 11, column 36
-- Equation name is 's2', location is LC056, type is output.
 s2      = DFFE( smf22 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 's3' = 'smf33' from file "adder8v3.tdf" line 11, column 36
-- Equation name is 's3', location is LC062, type is output.
 s3      = DFFE( smf23 $  GND, GLOBAL( clock),  VCC,  VCC,  VCC);

-- Node name is 's4' = 'ssf30' from file "adder8v3.tdf" line 11, column 48
-- Equation name is 's4', location is LC033, type is output.
 s4      = DFFE( _EQ007 $  pmf2, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ007 =  saf20 & !sbf20
         # !saf20 &  sbf20;

-- Node name is 's5' = 'ssf31' from file "adder8v3.tdf" line 11, column 48
-- Equation name is 's5', location is LC020, type is output.
 s5      = DFFE( _EQ008 $  saf21, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ008 =  pmf2 &  saf20 & !sbf21
         #  sbf20 & !sbf21 &  _X014
         # !saf20 &  sbf21 &  _X015
         # !pmf2 & !sbf20 &  sbf21;
  _X014  = EXP(!pmf2 & !saf20);
  _X015  = EXP( pmf2 &  sbf20);

-- Node name is 's6' = 'ssf32' from file "adder8v3.tdf" line 11, column 48
-- Equation name is 's6', location is LC017, type is output.
 s6      = DFFE( _EQ009 $  _EQ010, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ009 =  _X016 &  _X017;
  _X016  = EXP(!saf22 &  sbf22);
  _X017  = EXP( saf22 & !sbf22);
  _EQ010 =  _X018 &  _X019 &  _X020 &  _X021 &  _X022 &  _X023 &  _X024;
  _X018  = EXP( pmf2 &  saf20 &  sbf21);
  _X019  = EXP( pmf2 &  sbf20 &  sbf21);
  _X020  = EXP( saf20 &  sbf20 &  sbf21);
  _X021  = EXP( pmf2 &  saf21 &  sbf20);
  _X022  = EXP( pmf2 &  saf20 &  saf21);
  _X023  = EXP( saf20 &  saf21 &  sbf20);
  _X024  = EXP( saf21 &  sbf21);

-- Node name is 's7' = 'ssf33' from file "adder8v3.tdf" line 11, column 48
-- Equation name is 's7', location is LC035, type is output.
 s7      = DFFE( _EQ011 $  _EQ012, GLOBAL( clock),  VCC,  VCC,  VCC);
  _EQ011 =  _X025 &  _X026;
  _X025  = EXP(!saf23 &  sbf23);
  _X026  = EXP( saf23 & !sbf23);
  _EQ012 = !_LC034 & !_LC042 &  _X027 &  _X028 &  _X029 &  _X030 &  _X031;
  _X027  = EXP( pmf2 &  saf20 &  saf21 &  saf22);
  _X028  = EXP( saf20 &  saf21 &  saf22 &  sbf20);
  _X029  = EXP( saf21 &  sbf21 &  sbf22);
  _X030  = EXP( saf21 &  saf22 &  sbf21);
  _X031  = EXP( saf22 &  sbf22);

-- Node name is '|adder4:53|fa:41|~33~1' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC058', type is buried 
-- synthesized logic cell 
_LC058   = LCELL( _EQ013 $  GND);
  _EQ013 =  maf10 &  mbf10 &  mbf11 &  mbf12
         #  maf10 &  maf11 &  mbf10 &  mbf12
         #  maf10 &  maf12 &  mbf10 &  mbf11
         #  maf10 &  maf11 &  maf12 &  mbf10
         #  maf11 &  mbf11 &  mbf12;

-- Node name is '|adder4:68|fa:41|~33~1' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC034', type is buried 
-- synthesized logic cell 
_LC034   = LCELL( _EQ014 $  GND);
  _EQ014 =  pmf2 &  sbf20 &  sbf21 &  sbf22
         #  pmf2 &  saf20 &  sbf21 &  sbf22
         #  saf20 &  sbf20 &  sbf21 &  sbf22
         #  pmf2 &  saf21 &  sbf20 &  sbf22
         #  pmf2 &  saf20 &  saf21 &  sbf22;

-- Node name is '|adder4:68|fa:41|~33~2' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC042', type is buried 
-- synthesized logic cell 
_LC042   = LCELL( _EQ015 $  GND);
  _EQ015 =  saf20 &  saf21 &  sbf20 &  sbf22
         #  pmf2 &  saf22 &  sbf20 &  sbf21
         #  pmf2 &  saf20 &  saf22 &  sbf21
         #  saf20 &  saf22 &  sbf20 &  sbf21
         #  pmf2 &  saf21 &  saf22 &  sbf20;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                   z:\tec\lab6\adder8v3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,729K
