Project Information                                   z:\tec\lab6\adder8v2.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/16/2007 11:46:02

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


Untitled


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

adder8v2  EPM7064LC44-7    17       9        0      44      34          68 %

User Pins:                 17       9        0  



Project Information                                   z:\tec\lab6\adder8v2.rpt

** FILE HIERARCHY **



|adder4:53|
|adder4:53|fa:41|
|adder4:53|fa:47|
|adder4:53|fa:53|
|adder4:53|fa:59|
|adder4:68|
|adder4:68|fa:41|
|adder4:68|fa:47|
|adder4:68|fa:53|
|adder4:68|fa:59|


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

***** Logic for device 'adder8v2' compiled without errors.




Device: EPM7064LC44-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

                                               
                                               
                                               
                                               
                                               
                       V  G  G  G  G  G        
              b  b  b  C  N  N  N  N  N  s  s  
              3  4  5  C  D  D  D  D  D  1  2  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
      b2 |  7                                39 | RESERVED 
      b1 |  8                                38 | s3 
      b0 |  9                                37 | s0 
     GND | 10                                36 | RESERVED 
      a7 | 11                                35 | VCC 
     cin | 12         EPM7064LC44-7          34 | RESERVED 
      a1 | 13                                33 | RESERVED 
      a2 | 14                                32 | RESERVED 
     VCC | 15                                31 | RESERVED 
      a3 | 16                                30 | GND 
      s4 | 17                                29 | b7 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              a  a  c  s  G  V  b  a  a  s  s  
              5  6  o  7  N  C  6  0  4  6  5  
                    u     D  C                 
                    t                          
                                               
                                               
                                               
                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   8/ 8(100%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32    14/16( 87%)   8/ 8(100%)  13/16( 81%)  21/36( 58%) 
C:    LC33 - LC48    16/16(100%)   6/ 8( 75%)  16/16(100%)  26/36( 72%) 
D:    LC49 - LC64    14/16( 87%)   4/ 8( 50%)  15/16( 93%)  19/36( 52%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                            26/32     ( 81%)
Total logic cells used:                         44/64     ( 68%)
Total shareable expanders used:                 34/64     ( 53%)
Total Turbo logic cells used:                   44/64     ( 68%)
Total shareable expanders not available (n/a):  10/64     ( 15%)
Average fan-in:                                  3.04
Total fan-in:                                   134

Total input pins required:                      17
Total output pins required:                      9
Total bidirectional pins required:               0
Total logic cells required:                     44
Total flipflops required:                        0
Total product terms required:                  126
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          34

Synthesized logic cells:                         6/  64   (  9%)



Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  25   (35)  (C)      INPUT               0      0   0    0    0    0    1  a0
  13   (32)  (B)      INPUT               0      0   0    0    0    0    1  a1
  14   (30)  (B)      INPUT               0      0   0    0    0    0    1  a2
  16   (25)  (B)      INPUT               0      0   0    0    0    0    1  a3
  26   (36)  (C)      INPUT               0      0   0    0    0    0    1  a4
  18   (21)  (B)      INPUT               0      0   0    0    0    0    1  a5
  19   (20)  (B)      INPUT               0      0   0    0    0    0    1  a6
  11    (3)  (A)      INPUT               0      0   0    0    0    0    1  a7
   9    (4)  (A)      INPUT               0      0   0    0    0    0    1  b0
   8    (5)  (A)      INPUT               0      0   0    0    0    0    1  b1
   7    (8)  (A)      INPUT               0      0   0    0    0    0    1  b2
   6   (11)  (A)      INPUT               0      0   0    0    0    0    1  b3
   5   (14)  (A)      INPUT               0      0   0    0    0    0    1  b4
   4   (16)  (A)      INPUT               0      0   0    0    0    0    1  b5
  24   (33)  (C)      INPUT               0      0   0    0    0    0    1  b6
  29   (41)  (C)      INPUT               0      0   0    0    0    0    1  b7
  12    (1)  (A)      INPUT               0      0   0    0    0    0    7  cin


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  20     19    B     OUTPUT      t        5      0   1    0    9    0    0  cout
  37     53    D     OUTPUT      t        0      0   0    0    1    0    0  s0
  41     64    D     OUTPUT      t        0      0   0    0    1    0    0  s1
  40     62    D     OUTPUT      t        0      0   0    0    1    0    0  s2
  38     56    D     OUTPUT      t        0      0   0    0    1    0    0  s3
  17     24    B     OUTPUT      t        0      0   0    0    3    0    0  s4
  28     40    C     OUTPUT      t        3      0   1    0    5    0    0  s5
  27     37    C     OUTPUT      t        4      0   0    0    7    0    0  s6
  21     17    B     OUTPUT      t        7      0   0    0   11    0    0  s7


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     59    D       SOFT    s t        1      0   1    1    5    0    1  |adder4:53|fa:41|~33~1
   -     54    D       SOFT    s t        1      0   1    1    6    0    1  |adder4:53|fa:41|~33~2
   -     61    D       SOFT    s t        1      0   1    1    4    0    1  |adder4:53|fa:47|~33~1
   -     47    C       SOFT    s t        1      0   1    0    6    1    0  |adder4:68|fa:41|~33~1
 (32)    48    C       SOFT    s t        1      0   1    0    7    1    0  |adder4:68|fa:41|~33~2
   -     22    B       SOFT    s t        1      0   1    0    5    1    0  |adder4:68|fa:47|~33~1
 (39)    57    D      LCELL      t        0      0   0    1    0    0    8  maf10
 (36)    52    D      LCELL      t        0      0   0    1    0    0    7  maf11
 (34)    51    D      LCELL      t        0      0   0    1    0    0    4  maf12
   -     39    C      LCELL      t        0      0   0    1    0    0    2  maf13
   -     34    C      LCELL      t        0      0   0    1    0    0    8  mbf10
 (24)    33    C      LCELL      t        0      0   0    1    0    0    7  mbf11
 (25)    35    C      LCELL      t        0      0   0    1    0    0    5  mbf12
 (29)    41    C      LCELL      t        0      0   0    1    0    0    2  mbf13
 (33)    49    D      LCELL      t        5      0   1    1    8    4    3  pmf2
   -     43    C      LCELL      t        0      0   0    1    0    0    1  saf10
   -     44    C      LCELL      t        0      0   0    1    0    0    1  saf11
   -     45    C      LCELL      t        0      0   0    1    0    0    1  saf12
 (31)    46    C      LCELL      t        0      0   0    1    0    0    1  saf13
   -     50    D      LCELL      t        0      0   0    0    1    5    3  saf20
 (19)    20    B      LCELL      t        0      0   0    0    1    4    3  saf21
   -     26    B      LCELL      t        0      0   0    0    1    3    1  saf22
   -     31    B      LCELL      t        0      0   0    0    1    2    0  saf23
   -     23    B      LCELL      t        0      0   0    1    0    0    1  sbf10
 (13)    32    B      LCELL      t        0      0   0    1    0    0    1  sbf11
 (14)    30    B      LCELL      t        0      0   0    1    0    0    1  sbf12
   -     27    B      LCELL      t        0      0   0    1    0    0    1  sbf13
 (26)    36    C      LCELL      t        0      0   0    0    1    5    3  sbf20
 (18)    21    B      LCELL      t        0      0   0    0    1    4    3  sbf21
   -     18    B      LCELL      t        0      0   0    0    1    3    2  sbf22
 (16)    25    B      LCELL      t        0      0   0    0    1    2    0  sbf23
   -     58    D      LCELL      t        0      0   0    1    2    1    0  smf20
   -     38    C      LCELL      t        3      0   1    1    4    1    0  smf21
   -     42    C      LCELL      t        4      0   0    0    7    1    0  smf22
   -     60    D      LCELL      t        7      0   0    1   10    1    0  smf23


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                     Logic cells placed in LAB 'B'
        +--------------------------- LC22 |adder4:68|fa:47|~33~1
        | +------------------------- LC19 cout
        | | +----------------------- LC20 saf21
        | | | +--------------------- LC26 saf22
        | | | | +------------------- LC31 saf23
        | | | | | +----------------- LC23 sbf10
        | | | | | | +--------------- LC32 sbf11
        | | | | | | | +------------- LC30 sbf12
        | | | | | | | | +----------- LC27 sbf13
        | | | | | | | | | +--------- LC21 sbf21
        | | | | | | | | | | +------- LC18 sbf22
        | | | | | | | | | | | +----- LC25 sbf23
        | | | | | | | | | | | | +--- LC24 s4
        | | | | | | | | | | | | | +- LC17 s7
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC20 -> * * - - - - - - - - - - - * | - * * - | <-- saf21
LC26 -> - * - - - - - - - - - - - * | - * * - | <-- saf22
LC31 -> - * - - - - - - - - - - - * | - * - - | <-- saf23
LC32 -> - - - - - - - - - * - - - - | - * - - | <-- sbf11
LC30 -> - - - - - - - - - - * - - - | - * - - | <-- sbf12
LC27 -> - - - - - - - - - - - * - - | - * - - | <-- sbf13
LC21 -> * * - - - - - - - - - - - * | - * * - | <-- sbf21
LC18 -> - * - - - - - - - - - - - * | - * * - | <-- sbf22
LC25 -> - * - - - - - - - - - - - * | - * - - | <-- sbf23

Pin
5    -> - - - - - * - - - - - - - - | - * - - | <-- b4
4    -> - - - - - - * - - - - - - - | - * - - | <-- b5
24   -> - - - - - - - * - - - - - - | - * - - | <-- b6
29   -> - - - - - - - - * - - - - - | - * - - | <-- b7
LC47 -> - - - - - - - - - - - - - * | - * - - | <-- |adder4:68|fa:41|~33~1
LC48 -> - - - - - - - - - - - - - * | - * - - | <-- |adder4:68|fa:41|~33~2
LC49 -> * * - - - - - - - - - - * * | - * * - | <-- pmf2
LC44 -> - - * - - - - - - - - - - - | - * - - | <-- saf11
LC45 -> - - - * - - - - - - - - - - | - * - - | <-- saf12
LC46 -> - - - - * - - - - - - - - - | - * - - | <-- saf13
LC50 -> * * - - - - - - - - - - * * | - * * - | <-- saf20
LC36 -> * * - - - - - - - - - - * * | - * * - | <-- sbf20


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC47 |adder4:68|fa:41|~33~1
        | +----------------------------- LC48 |adder4:68|fa:41|~33~2
        | | +--------------------------- LC39 maf13
        | | | +------------------------- LC34 mbf10
        | | | | +----------------------- LC33 mbf11
        | | | | | +--------------------- LC35 mbf12
        | | | | | | +------------------- LC41 mbf13
        | | | | | | | +----------------- LC43 saf10
        | | | | | | | | +--------------- LC44 saf11
        | | | | | | | | | +------------- LC45 saf12
        | | | | | | | | | | +----------- LC46 saf13
        | | | | | | | | | | | +--------- LC36 sbf20
        | | | | | | | | | | | | +------- LC38 smf21
        | | | | | | | | | | | | | +----- LC42 smf22
        | | | | | | | | | | | | | | +--- LC40 s5
        | | | | | | | | | | | | | | | +- LC37 s6
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC34 -> - - - - - - - - - - - - * * - - | - - * * | <-- mbf10
LC33 -> - - - - - - - - - - - - * * - - | - - * * | <-- mbf11
LC35 -> - - - - - - - - - - - - - * - - | - - * * | <-- mbf12
LC36 -> * * - - - - - - - - - - - - * * | - * * - | <-- sbf20

Pin
16   -> - - * - - - - - - - - - - - - - | - - * - | <-- a3
26   -> - - - - - - - * - - - - - - - - | - - * - | <-- a4
18   -> - - - - - - - - * - - - - - - - | - - * - | <-- a5
19   -> - - - - - - - - - * - - - - - - | - - * - | <-- a6
11   -> - - - - - - - - - - * - - - - - | - - * - | <-- a7
9    -> - - - * - - - - - - - - - - - - | - - * - | <-- b0
8    -> - - - - * - - - - - - - - - - - | - - * - | <-- b1
7    -> - - - - - * - - - - - - - - - - | - - * - | <-- b2
6    -> - - - - - - * - - - - - - - - - | - - * - | <-- b3
12   -> - - - - - - - - - - - - * - - - | - - * * | <-- cin
LC61 -> - - - - - - - - - - - - - * - - | - - * - | <-- |adder4:53|fa:47|~33~1
LC22 -> - - - - - - - - - - - - - - - * | - - * - | <-- |adder4:68|fa:47|~33~1
LC57 -> - - - - - - - - - - - - * * - - | - - * * | <-- maf10
LC52 -> - - - - - - - - - - - - * * - - | - - * * | <-- maf11
LC51 -> - - - - - - - - - - - - - * - - | - - * * | <-- maf12
LC49 -> * * - - - - - - - - - - - - * - | - * * - | <-- pmf2
LC50 -> * * - - - - - - - - - - - - * * | - * * - | <-- saf20
LC20 -> * * - - - - - - - - - - - - * * | - * * - | <-- saf21
LC26 -> - * - - - - - - - - - - - - - * | - * * - | <-- saf22
LC23 -> - - - - - - - - - - - * - - - - | - - * - | <-- sbf10
LC21 -> * * - - - - - - - - - - - - * * | - * * - | <-- sbf21
LC18 -> * * - - - - - - - - - - - - - * | - * * - | <-- sbf22


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                     Logic cells placed in LAB 'D'
        +--------------------------- LC59 |adder4:53|fa:41|~33~1
        | +------------------------- LC54 |adder4:53|fa:41|~33~2
        | | +----------------------- LC61 |adder4:53|fa:47|~33~1
        | | | +--------------------- LC57 maf10
        | | | | +------------------- LC52 maf11
        | | | | | +----------------- LC51 maf12
        | | | | | | +--------------- LC49 pmf2
        | | | | | | | +------------- LC50 saf20
        | | | | | | | | +----------- LC58 smf20
        | | | | | | | | | +--------- LC60 smf23
        | | | | | | | | | | +------- LC53 s0
        | | | | | | | | | | | +----- LC64 s1
        | | | | | | | | | | | | +--- LC62 s2
        | | | | | | | | | | | | | +- LC56 s3
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC59 -> - - - - - - - - - * - - - - | - - - * | <-- |adder4:53|fa:41|~33~1
LC54 -> - - - - - - - - - * - - - - | - - - * | <-- |adder4:53|fa:41|~33~2
LC57 -> * * * - - - * - * * - - - - | - - * * | <-- maf10
LC52 -> * * * - - - * - - * - - - - | - - * * | <-- maf11
LC51 -> - * - - - - * - - * - - - - | - - * * | <-- maf12
LC58 -> - - - - - - - - - - * - - - | - - - * | <-- smf20
LC60 -> - - - - - - - - - - - - - * | - - - * | <-- smf23

Pin
25   -> - - - * - - - - - - - - - - | - - - * | <-- a0
13   -> - - - - * - - - - - - - - - | - - - * | <-- a1
14   -> - - - - - * - - - - - - - - | - - - * | <-- a2
12   -> * * * - - - * - * * - - - - | - - * * | <-- cin
LC39 -> - - - - - - * - - * - - - - | - - - * | <-- maf13
LC34 -> * * * - - - * - * * - - - - | - - * * | <-- mbf10
LC33 -> * * * - - - * - - * - - - - | - - * * | <-- mbf11
LC35 -> * * - - - - * - - * - - - - | - - * * | <-- mbf12
LC41 -> - - - - - - * - - * - - - - | - - - * | <-- mbf13
LC43 -> - - - - - - - * - - - - - - | - - - * | <-- saf10
LC38 -> - - - - - - - - - - - * - - | - - - * | <-- smf21
LC42 -> - - - - - - - - - - - - * - | - - - * | <-- smf22


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          z:\tec\lab6\adder8v2.rpt
adder8v2

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
a4       : INPUT;
a5       : INPUT;
a6       : INPUT;
a7       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
b4       : INPUT;
b5       : INPUT;
b6       : INPUT;
b7       : INPUT;
cin      : INPUT;

-- Node name is 'cout' = 'psf3' from file "adder8v2.tdf" line 10, column 116
-- Equation name is 'cout', location is LC019, type is output.
 cout    = LCELL( _EQ001 $  GND);
  _EQ001 =  saf20 &  sbf20 &  _X001 &  _X002 &  _X003
         #  pmf2 &  _X001 &  _X002 &  _X003 &  _X004
         #  saf21 &  sbf21 &  _X001 &  _X003
         #  saf22 &  sbf22 &  _X003
         #  saf23 &  sbf23;
  _X001  = EXP(!saf22 & !sbf22);
  _X002  = EXP(!saf21 & !sbf21);
  _X003  = EXP(!saf23 & !sbf23);
  _X004  = EXP(!saf20 & !sbf20);

-- Node name is 'maf10' from file "adder8v2.tdf" line 10, column 6
-- Equation name is 'maf10', location is LC057, type is buried.
maf10    = LCELL( a0 $  GND);

-- Node name is 'maf11' from file "adder8v2.tdf" line 10, column 6
-- Equation name is 'maf11', location is LC052, type is buried.
maf11    = LCELL( a1 $  GND);

-- Node name is 'maf12' from file "adder8v2.tdf" line 10, column 6
-- Equation name is 'maf12', location is LC051, type is buried.
maf12    = LCELL( a2 $  GND);

-- Node name is 'maf13' from file "adder8v2.tdf" line 10, column 6
-- Equation name is 'maf13', location is LC039, type is buried.
maf13    = LCELL( a3 $  GND);

-- Node name is 'mbf10' from file "adder8v2.tdf" line 10, column 18
-- Equation name is 'mbf10', location is LC034, type is buried.
mbf10    = LCELL( b0 $  GND);

-- Node name is 'mbf11' from file "adder8v2.tdf" line 10, column 18
-- Equation name is 'mbf11', location is LC033, type is buried.
mbf11    = LCELL( b1 $  GND);

-- Node name is 'mbf12' from file "adder8v2.tdf" line 10, column 18
-- Equation name is 'mbf12', location is LC035, type is buried.
mbf12    = LCELL( b2 $  GND);

-- Node name is 'mbf13' from file "adder8v2.tdf" line 10, column 18
-- Equation name is 'mbf13', location is LC041, type is buried.
mbf13    = LCELL( b3 $  GND);

-- Node name is 'pmf2' from file "adder8v2.tdf" line 10, column 62
-- Equation name is 'pmf2', location is LC049, type is buried.
pmf2     = LCELL( _EQ002 $  GND);
  _EQ002 =  maf10 &  mbf10 &  _X005 &  _X006 &  _X007
         #  cin &  _X005 &  _X006 &  _X007 &  _X008
         #  maf11 &  mbf11 &  _X005 &  _X007
         #  maf12 &  mbf12 &  _X007
         #  maf13 &  mbf13;
  _X005  = EXP(!maf12 & !mbf12);
  _X006  = EXP(!maf11 & !mbf11);
  _X007  = EXP(!maf13 & !mbf13);
  _X008  = EXP(!maf10 & !mbf10);

-- Node name is 'saf10' from file "adder8v2.tdf" line 10, column 30
-- Equation name is 'saf10', location is LC043, type is buried.
saf10    = LCELL( a4 $  GND);

-- Node name is 'saf11' from file "adder8v2.tdf" line 10, column 30
-- Equation name is 'saf11', location is LC044, type is buried.
saf11    = LCELL( a5 $  GND);

-- Node name is 'saf12' from file "adder8v2.tdf" line 10, column 30
-- Equation name is 'saf12', location is LC045, type is buried.
saf12    = LCELL( a6 $  GND);

-- Node name is 'saf13' from file "adder8v2.tdf" line 10, column 30
-- Equation name is 'saf13', location is LC046, type is buried.
saf13    = LCELL( a7 $  GND);

-- Node name is 'saf20' from file "adder8v2.tdf" line 10, column 72
-- Equation name is 'saf20', location is LC050, type is buried.
saf20    = LCELL( saf10 $  GND);

-- Node name is 'saf21' from file "adder8v2.tdf" line 10, column 72
-- Equation name is 'saf21', location is LC020, type is buried.
saf21    = LCELL( saf11 $  GND);

-- Node name is 'saf22' from file "adder8v2.tdf" line 10, column 72
-- Equation name is 'saf22', location is LC026, type is buried.
saf22    = LCELL( saf12 $  GND);

-- Node name is 'saf23' from file "adder8v2.tdf" line 10, column 72
-- Equation name is 'saf23', location is LC031, type is buried.
saf23    = LCELL( saf13 $  GND);

-- Node name is 'sbf10' from file "adder8v2.tdf" line 10, column 42
-- Equation name is 'sbf10', location is LC023, type is buried.
sbf10    = LCELL( b4 $  GND);

-- Node name is 'sbf11' from file "adder8v2.tdf" line 10, column 42
-- Equation name is 'sbf11', location is LC032, type is buried.
sbf11    = LCELL( b5 $  GND);

-- Node name is 'sbf12' from file "adder8v2.tdf" line 10, column 42
-- Equation name is 'sbf12', location is LC030, type is buried.
sbf12    = LCELL( b6 $  GND);

-- Node name is 'sbf13' from file "adder8v2.tdf" line 10, column 42
-- Equation name is 'sbf13', location is LC027, type is buried.
sbf13    = LCELL( b7 $  GND);

-- Node name is 'sbf20' from file "adder8v2.tdf" line 10, column 84
-- Equation name is 'sbf20', location is LC036, type is buried.
sbf20    = LCELL( sbf10 $  GND);

-- Node name is 'sbf21' from file "adder8v2.tdf" line 10, column 84
-- Equation name is 'sbf21', location is LC021, type is buried.
sbf21    = LCELL( sbf11 $  GND);

-- Node name is 'sbf22' from file "adder8v2.tdf" line 10, column 84
-- Equation name is 'sbf22', location is LC018, type is buried.
sbf22    = LCELL( sbf12 $  GND);

-- Node name is 'sbf23' from file "adder8v2.tdf" line 10, column 84
-- Equation name is 'sbf23', location is LC025, type is buried.
sbf23    = LCELL( sbf13 $  GND);

-- Node name is 'smf20' from file "adder8v2.tdf" line 10, column 54
-- Equation name is 'smf20', location is LC058, type is buried.
smf20    = LCELL( _EQ003 $  cin);
  _EQ003 =  maf10 & !mbf10
         # !maf10 &  mbf10;

-- Node name is 'smf21' from file "adder8v2.tdf" line 10, column 54
-- Equation name is 'smf21', location is LC038, type is buried.
smf21    = LCELL( _EQ004 $  maf11);
  _EQ004 =  cin &  maf10 & !mbf11
         #  mbf10 & !mbf11 &  _X009
         # !maf10 &  mbf11 &  _X010
         # !cin & !mbf10 &  mbf11;
  _X009  = EXP(!cin & !maf10);
  _X010  = EXP( cin &  mbf10);

-- Node name is 'smf22' from file "adder8v2.tdf" line 10, column 54
-- Equation name is 'smf22', location is LC042, type is buried.
smf22    = LCELL( _EQ005 $  _EQ006);
  _EQ005 =  _X011 &  _X012;
  _X011  = EXP(!maf12 &  mbf12);
  _X012  = EXP( maf12 & !mbf12);
  _EQ006 = !_LC061 &  _X013 &  _X014;
  _X013  = EXP( maf10 &  maf11 &  mbf10);
  _X014  = EXP( maf11 &  mbf11);

-- Node name is 'smf23' from file "adder8v2.tdf" line 10, column 54
-- Equation name is 'smf23', location is LC060, type is buried.
smf23    = LCELL( _EQ007 $  _EQ008);
  _EQ007 =  _X015 &  _X016;
  _X015  = EXP(!maf13 &  mbf13);
  _X016  = EXP( maf13 & !mbf13);
  _EQ008 = !_LC054 & !_LC059 &  _X017 &  _X018 &  _X019 &  _X020 &  _X021;
  _X017  = EXP( cin &  maf10 &  maf11 &  maf12);
  _X018  = EXP( maf10 &  maf11 &  maf12 &  mbf10);
  _X019  = EXP( maf11 &  mbf11 &  mbf12);
  _X020  = EXP( maf11 &  maf12 &  mbf11);
  _X021  = EXP( maf12 &  mbf12);

-- Node name is 's0' = 'smf30' from file "adder8v2.tdf" line 10, column 96
-- Equation name is 's0', location is LC053, type is output.
 s0      = LCELL( smf20 $  GND);

-- Node name is 's1' = 'smf31' from file "adder8v2.tdf" line 10, column 96
-- Equation name is 's1', location is LC064, type is output.
 s1      = LCELL( smf21 $  GND);

-- Node name is 's2' = 'smf32' from file "adder8v2.tdf" line 10, column 96
-- Equation name is 's2', location is LC062, type is output.
 s2      = LCELL( smf22 $  GND);

-- Node name is 's3' = 'smf33' from file "adder8v2.tdf" line 10, column 96
-- Equation name is 's3', location is LC056, type is output.
 s3      = LCELL( smf23 $  GND);

-- Node name is 's4' = 'ssf30' from file "adder8v2.tdf" line 10, column 108
-- Equation name is 's4', location is LC024, type is output.
 s4      = LCELL( _EQ009 $  pmf2);
  _EQ009 =  saf20 & !sbf20
         # !saf20 &  sbf20;

-- Node name is 's5' = 'ssf31' from file "adder8v2.tdf" line 10, column 108
-- Equation name is 's5', location is LC040, type is output.
 s5      = LCELL( _EQ010 $  saf21);
  _EQ010 =  pmf2 &  saf20 & !sbf21
         #  sbf20 & !sbf21 &  _X022
         # !saf20 &  sbf21 &  _X023
         # !pmf2 & !sbf20 &  sbf21;
  _X022  = EXP(!pmf2 & !saf20);
  _X023  = EXP( pmf2 &  sbf20);

-- Node name is 's6' = 'ssf32' from file "adder8v2.tdf" line 10, column 108
-- Equation name is 's6', location is LC037, type is output.
 s6      = LCELL( _EQ011 $  _EQ012);
  _EQ011 =  _X024 &  _X025;
  _X024  = EXP(!saf22 &  sbf22);
  _X025  = EXP( saf22 & !sbf22);
  _EQ012 = !_LC022 &  _X026 &  _X027;
  _X026  = EXP( saf20 &  saf21 &  sbf20);
  _X027  = EXP( saf21 &  sbf21);

-- Node name is 's7' = 'ssf33' from file "adder8v2.tdf" line 10, column 108
-- Equation name is 's7', location is LC017, type is output.
 s7      = LCELL( _EQ013 $  _EQ014);
  _EQ013 =  _X028 &  _X029;
  _X028  = EXP(!saf23 &  sbf23);
  _X029  = EXP( saf23 & !sbf23);
  _EQ014 = !_LC047 & !_LC048 &  _X030 &  _X031 &  _X032 &  _X033 &  _X034;
  _X030  = EXP( pmf2 &  saf20 &  saf21 &  saf22);
  _X031  = EXP( saf20 &  saf21 &  saf22 &  sbf20);
  _X032  = EXP( saf21 &  sbf21 &  sbf22);
  _X033  = EXP( saf21 &  saf22 &  sbf21);
  _X034  = EXP( saf22 &  sbf22);

-- Node name is '|adder4:53|fa:41|~33~1' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC059', type is buried 
-- synthesized logic cell 
_LC059   = LCELL( _EQ015 $  GND);
  _EQ015 =  cin &  mbf10 &  mbf11 &  mbf12
         #  cin &  maf10 &  mbf11 &  mbf12
         #  maf10 &  mbf10 &  mbf11 &  mbf12
         #  cin &  maf11 &  mbf10 &  mbf12
         #  cin &  maf10 &  maf11 &  mbf12;

-- Node name is '|adder4:53|fa:41|~33~2' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC054', type is buried 
-- synthesized logic cell 
_LC054   = LCELL( _EQ016 $  GND);
  _EQ016 =  maf10 &  maf11 &  mbf10 &  mbf12
         #  cin &  maf12 &  mbf10 &  mbf11
         #  cin &  maf10 &  maf12 &  mbf11
         #  maf10 &  maf12 &  mbf10 &  mbf11
         #  cin &  maf11 &  maf12 &  mbf10;

-- Node name is '|adder4:53|fa:47|~33~1' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC061', type is buried 
-- synthesized logic cell 
_LC061   = LCELL( _EQ017 $  GND);
  _EQ017 =  cin &  mbf10 &  mbf11
         #  cin &  maf10 &  mbf11
         #  maf10 &  mbf10 &  mbf11
         #  cin &  maf11 &  mbf10
         #  cin &  maf10 &  maf11;

-- Node name is '|adder4:68|fa:41|~33~1' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC047', type is buried 
-- synthesized logic cell 
_LC047   = LCELL( _EQ018 $  GND);
  _EQ018 =  pmf2 &  sbf20 &  sbf21 &  sbf22
         #  pmf2 &  saf20 &  sbf21 &  sbf22
         #  saf20 &  sbf20 &  sbf21 &  sbf22
         #  pmf2 &  saf21 &  sbf20 &  sbf22
         #  pmf2 &  saf20 &  saf21 &  sbf22;

-- Node name is '|adder4:68|fa:41|~33~2' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC048', type is buried 
-- synthesized logic cell 
_LC048   = LCELL( _EQ019 $  GND);
  _EQ019 =  saf20 &  saf21 &  sbf20 &  sbf22
         #  pmf2 &  saf22 &  sbf20 &  sbf21
         #  pmf2 &  saf20 &  saf22 &  sbf21
         #  saf20 &  saf22 &  sbf20 &  sbf21
         #  pmf2 &  saf21 &  saf22 &  sbf20;

-- Node name is '|adder4:68|fa:47|~33~1' from file "fa.tdf" line 9, column 14
-- Equation name is '_LC022', type is buried 
-- synthesized logic cell 
_LC022   = LCELL( _EQ020 $  GND);
  _EQ020 =  pmf2 &  sbf20 &  sbf21
         #  pmf2 &  saf20 &  sbf21
         #  saf20 &  sbf20 &  sbf21
         #  pmf2 &  saf21 &  sbf20
         #  pmf2 &  saf20 &  saf21;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                   z:\tec\lab6\adder8v2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,490K
